Semiconductor PCB Flow Lab
Semiconductor PCB Flow Lab
Factory Physics capstone · Large-panel PCB line · 12 process centers

The line can ship today's volume in two days. It takes 34.

Process route

Each card shows a process center's capacity in panels per day. The bar shows its utilization at today's 1,400 panels/day.

≥ 3,000 target2,500–3,000< 2,500

Capacity vs. demand

Panels per day. Line capacity is set by the slowest center.

Today's output 1,400Target 3,000

Diagnosis

What the corrected model says about the as-is line.

What changed from the 2024 workbook

The original Excel model was rebuilt and checked against the case data. Seven fixes changed the answer: the bottleneck moves from Procoat to Internal Circuitize (by a 3% margin, which is why it "floats"), raw process time rises from 30.4 h to 33.9 h, and the "current TH" curve is replaced by the single observed point. The full list, with reasons, is in Guide › Corrections log.